One or more aspects relate in general to data processing systems, and in particular, to tracing data from an asynchronous interface for debugging purposes.
Asynchronous data transfers have become very common in many integrated circuit devices, such as application-specific integrated circuits (ASICs) and system-on-chips (SoCs). In particular, various components or subsystems utilized for the construction of an integrated circuit may independently operate at different frequencies, such as in microprocessors and micro-controllers, where certain components or subsystems have a faster rate of operation than the operating frequencies of other system components or subsystems. Therefore, typically, it is desirable to devise integrated circuits with the ability to support multiple domains, which may operate at different frequencies.
For instance, many integrated circuits include a number of electronic circuits referred to as “clocked logic domains” that operate independently based on electrical “timing” or “clock” signals. Such clock signals are used to control and coordinate the activities of various components or subsystems. Since there will not be a fixed relationship between the active edge of a launch clock and a capture clock, there is a possibility of having setup or hold violations in the capture flip-flop, causing meta-stability. To avoid meta-stability in asynchronous data transfer, a commonly adopted technique is to double latch (also called double stage synchronization, or double flopping) the clock domain crossing signal at the receive domain clock frequency. Double flopping involves passing an asynchronous signal through a pair of edge triggered D-Flip-flops or some equivalent storage element. If the receiving clock frequency is considerably less than the transmitting clock frequency, there is a huge latency involved in the double flopping process, often up to 20 or more clock cycles in the higher frequency domain. This situation frequently arises with slower devices, like a Flash Memory controller, being used in ASICs that have a majority of the components running at a much higher clock frequency. Any reduction in the clock domain-crossing overhead significantly reduces the data transfer latencies and increases the overall system performance.
A variety of devices and methods are used in conjunction with the use of debug trace data in a system. The trace data can be passed between several different components in the circuit. Established protocols allow the different components to communicate with each other. One example involves a microprocessor circuit system. As the demand for more powerful and/or faster systems increases, design constraints, such as power consumption and heat dissipation, can become increasingly problematic.
U.S. Pat. No. 8,132,036 B2, hereby incorporated herein by reference in its entirety, discloses a method and an interfacing circuit for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock frequency C2. In accordance with this, data is transmitted from the first domain, through an interfacing circuitry, and to the second domain. The interfacing circuitry includes a synchronization section that operates at a third frequency C3, wherein C3 is a whole number multiple of C2. For example, C3 may be an even whole number multiple of C2.
Thus in U.S. Pat. No. 8,132,036 B2, a clock signal A is used to operate the second clock domain at frequency C2, and a clock signal B is used to operate the second section of the interfacing circuitry at frequency C3. Each of the clock signals A and B have regular, active edge portions, and each occurrence of one of the active edge portions of clock signal A is clock aligned with one of the active edge portions of clock signal B. Clock signals A and B are source synchronized.
In U.S. Pat. No. 8,132,036 B2, the synchronization section of the interfacing circuitry includes first and second registers. Clock signal B is applied to both the first and second registers to operate these registers at frequency C3. In an asynchronous data transfer, the higher clock frequency that launches data may be C1 and the lower clock frequency that captures data may be C2. In accordance with this, the interface flip-flops used for double flopping run at a higher source synchronous clock frequency C3. C3 is source synchronized with the low frequency clock C2, and C3 and C2 have a common active edge and will be considered synchronous.